1. Field of the Invention
The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of partitioning an integrated circuit design into a smaller address space to increase efficiency of physical design verification tools.
2. Description of Related Art
Physical design verification tools are typically run on 32-bit processors and 64-bit processors to verify integrated circuit designs represented by GDS2 files. The 32-bit processors have an address space that can accommodate integrated circuit designs up to 3.5 gigabytes in size, while the 64-bit processors have a larger address space that affords the capability of accommodating integrated designs larger than 3.5 gigabytes.